The present invention relates to a clocked CMOS circuit wherein the gates of p- and n-channel switching transistors ("n- and p-switching transistors") and/or the gates of at least one n-channel-/p-channel-transistor pair used as a CMOS switch ("transistor pair") are each supplied with one of two mutually inverse clock signals ("n-clock and p-clock").
As is well known (e.g., as disclosed in U.S. Pat. No. 3,457,435), the simplest CMOS switch of this kind is the CMOS transmission gate, in which the controlled current paths of the two transistors of the transistor path are connected in parallel, and in which, to bias the two transistors on and off, the n-clock is applied to the gate of the n-channel transistor, and the p-clock to the gate of the p-channel transistor.
An exemplary clocked CMOS circuit is disclosed in European Patent Application EP-A 115 834, particularly in FIGS. 2c, 3a, 3b, 3f, and 3g in accordance with the description on pages 4 to 8. According to that description, a clock race problem occurs in such CMOS circuits, i.e., a condition in which useful signals are switched at a rate higher than the clock rate, which is due to the overlap of the edges of the clock signals. In the above-referenced European Patent Application, a solution to this problem is seen in a clocked CMOS circuit in which the individual subcircuits, particularly logic gates, are specifically designed with a view to eliminating clock races. The inventors have discovered that the edge overlap also results in short interference pulses at the outputs of the transistor pairs which may simulate useful signals. This is disadvantageous particularly if several such pairs are combined to form a switching network, e.g., by connecting the controlled current paths of several n-channel transistors in series to form a first series combination, by connecting the controlled current paths of the same number of p-channel transistors in series to form a second series combination, and by connecting the two series combinations in parallel.
The object of the invention as claimed is to avoid such interference pulses.